DFT Engineer Intern
CHS OU Ambarella (Shanghai) Company Ltd
Apply to this job US Headquarters Until 8/22/2026 First posted March 18, 2026 Last posted March 18, 2026
Job description
AI Vision Processors For Edge Applications
Our solutions make cameras smarter by extracting valuable data from high-resolution video streams.
Job Description
Position Responsibilities:
- Logic Design to support DFT features
- Automate DFT Flows (Scan, Compression & MBIST) used for complex multi-million gate SoC
- Verification of DFT Logic and analysis of fault coverage
- Timing analysis for DFT Modes
Minimum Requirements:
- MSEE in Electrical / Computer Engineering
- Knowledge of DFT fundamentals
- Knowledge of Logic design & Static timing analysis
- Knowledge of Verilog and any scripting language
About this role
Summary
Support DFT logic design, verification, and timing analysis for complex SoC designs.
Job title
DFT Engineer Intern
Experience level
intern
Industry
technology
Location requirements
US headquarters, on-site role
Salary
Not specified
Management role
No
Skills & keywords
Required skills
DFT fundamentalslogic designstatic timing analysisVerilogscripting
Preferred skills
None specified
Specializations
DFTlogic designtiming analysisVerilogautomation
Locations
Structured locations inferred from the posting.
Unknown location
On-site
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