Design Verification Engineer

Herzliya Until 9/22/2026 5+ years exp First posted July 24, 2026 Last posted July 24, 2026
Job description

In this visible role, you will be responsible for taking part of a SoC verification process of a large scale SoC. You will develop verification test plans, tools, test benches, protocol monitors, and high-coverage stimulus vectors. Apply advanced techniques to achieve verification with the highest quality, productivity, and time-to-market. You will work closely with the design team to ensure timely delivery of quality designs. Working with methods to accelerate verification time. The position is relevant to all Apple sites: Herzliya, Haifa and Jerusalem

Description

Imagine what you could do here. At Apple, new ideas have a way of becoming great products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish.
The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies to our practices - strengthening our dedication to leave the world better than we found it. Join us to help deliver the next groundbreaking Apple products.

Minimum Qualifications

5+ years of experience in SoC or IP verification
Advanced knowledge of SoC architecture/design, in-depth knowledge of verification flows and broad system view
Expected to have a deep understanding and shown experience in advanced verification processes, including coverage driven and formal methods
Extensive experience with SystemVerilog and UVM
Experience with verification infrastructure development
Knowledge of storage IPs and control oriented design - an advantage
Knowledge of formal, hardware acceleration – an advantage
Scripting and programming experience using several of the following: Perl, Python, Verilog, SystemVerilog, C, C++, and TCL

Preferred Qualifications

B.Sc / M.Sc in Electrical or Computer Engineering

About this role

Summary

Develop and implement verification plans, tools, test benches, and protocols for SoC.

Job title

Design Verification Engineer

Experience level

5+ years

Minimum experience

5+ years exp

Industry

technology

Location requirements

Herzliya, remote work not specified

Salary

Not specified

Management role

No

Skills & keywords

Required skills

SystemVerilogUVMverification workflowsPerlPythonVerilogC++

Preferred skills

formal verificationhardware accelerationstorage IPs

Specializations

verificationSystemVerilogUVMformal methodsverification infrastructure
Locations

Structured locations inferred from the posting.

Herzliya, Israel

Work arrangement unknown City