Debug SoC Design Engineer

Irvine San Diego Until 9/22/2026 First posted July 24, 2026 Last posted July 24, 2026
Job description

Come and join Apple’s growing wireless silicon development team. Our wireless SoC organization is responsible for all aspects of wireless silicon development, emphasizing highly energy-efficient design and new technologies that transform the user experience at the product level. All of this is driven by a world-class vertically integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. If you enjoy a fast-paced and challenging environment, collaborate with people across different functional areas, and thrive during crisis times, we encourage you to apply.

Description

In this role you will work on a small team designing CPU-based subsystems for high performance, low power wireless SoCs. You will work closely with SoC architects and IP developers to define debug features that meet the power, performance, and area goals.

You will own the design for the debug and trace hub. You will collaborate with other designers to ensure their subsystems implement the necessary debug features. You will guide validation engineers in the use of such features to diagnose issues. This is a highly visible role, where you will be at the center of the ASIC debug efforts, collaborating with all fields, with a critical impact in getting leading-edge products launched to delight millions of customers.

Minimum Qualifications

Minimum requirement of bachelor's degree

Preferred Qualifications

Familiarity with the ASIC design flow.
Knowledge of digital design, SoC architecture, and HDL languages like Verilog.
Familiarity with design methodologies and industry standard EDA tools.
Knowledge and understanding of microprocessor debug such as CoreSight and other debug techniques.
Shown experience writing micro-architecture specifications and converting them to design.
Experience with AXI/AHB bus fabric and processor sub-systems.
Understanding of UPF and low-power design & implementation techniques.
Self-starter and willingness to learn.

About this role

Summary

Design CPU subsystems and debug features for energy-efficient wireless SoCs.

Job title

Debug SoC Design Engineer

Experience level

entry level

Industry

software

Location requirements

Irvine, San Diego, Sunnyvale; no remote work.

Salary

Not specified

Management role

No

Skills & keywords

Required skills

Verilogmicroprocessor debugASIC designEDA toolsHDL

Preferred skills

ASIC design flowSoC architectureAXI/AHBUPFdebug techniques

Specializations

ASIC designmicroprocessor debugHDLSoC architecturepower management
Locations

Structured locations inferred from the posting.

Irvine, CA, USA

On-site City

San Diego, CA, USA

On-site City

Sunnyvale, CA, USA

On-site City