Custom Timing and Verification CAD Engineer

Apple's custom silicon is among the most sophisticated in the world — and getting it right requires rigorous transistor-level timing verification and formal verification at every step. Our Custom Timing CAD team builds and owns the flows, tools, and methodologies that make that verification possible. We are looking for an entry-level engineer who is eager to learn, technically curious, and excited to work at the intersection of circuit design and CAD engineering.

Description

In this role, you will support and develop flows for two of the most critical sign-off disciplines in custom IC design — transistor-level timing verification using NanoTime and formal verification using ESP. You will partner closely with analog and digital designers across multiple programs and technology nodes, helping them set up flows, debug issues, and achieve clean sign-off. The work you do will directly shape the quality and schedule of Apple's most advanced chips.

Minimum Qualifications

BS degree (MS preferred) in Electrical Engineering, Computer Engineering, Computer Science, or related field
Programming or scripting experience in Perl, Python, TCL, or similar language
Foundational understanding of digital or custom IC design at transistor level and static timing analysis through coursework or internship experience

Preferred Qualifications

Exposure to tools such as NanoTime, ESP, PrimeTime, or HSPICE is a plus
Knowledge of dynamic logic, memory arrays, or mixed-signal circuit techniques
Familiarity with SPICE netlists, device models, and parasitic extraction formats such as DSPF or SPF
Knowledge of formal verification tools and concepts and experience with SystemVerilog RTL
Interest in AI/ML-driven innovation for CAD workflows
Strong communicator who can accurately describe technical issues and follow them through to resolution
Highly motivated and able to work independently in a fast-paced environment