Custom Circuits Design Verification Engineer

Does making the next great technology product excite you? At Apple, we work every single day to craft products that enrich peopleʼs lives. Our new ideas have a way of becoming great products, services, and customer experiences very quickly. Design Verification Engineers at Apple are responsible for verifying the functionality and performance of Appleʼs premier SoCs that make their way into Apple products. We are looking for a Design Verification Engineer who will enable bug-free first silicon for all the Digital custom IPs we deliver to the many SoCs that Apple produces.

Description

In this role as a Custom Circuits DV Engineer, you will be working with the digital custom circuits team to ensure that all pre-silicon deliveries of custom IPs to all Apple SoC’s are bug-free. This requires you to review design and architecture specifications and understand the use cases and corner conditions. Furthermore, you will be required to translate these specifications into test benches that include all the respective components such as stimulus, checkers, assertions, trackers, and coverage. You will also work closely with both the custom circuit designers and RTL designers to understand the functionality and performance goals of the design. We also require additional responsibilities such as running and triaging regressions, tracking bugs, and analyzing coverage to achieve high quality results. In this highly visible role, you will be at the center of a SoC design effort collaborating with all teams, with a critical impact on getting bug-free functional products to market quickly.

Minimum Qualifications

BS degree plus minimum of 10 years of relevant industry experience

Preferred Qualifications

DV skills including, but not limited to, random verification process, functional coverage, code coverage, assertion methodology & philosophy.
Knowledge of Verilog/System Verilog, digital simulation and debug tools.
At least one scripting language, such as Perl or Python.
Knowledge of behavioral and structural RTL coding especially as it pertains to SRAM, register file, and other custom circuit designs. Plus knowledge of FPGA and emulation challenges related to RTL coding and verification is desirable.
Knowledge of industry standard design tools, such as ESPCV and/or LEC.
Knowledge of regression and revision control tools.
DFT (ATPG/MBIST) knowledge is desirable.