CPU Design Timing Engineer

Santa Clara Until 9/22/2026 3+ years exp First posted July 24, 2026 Last posted July 24, 2026
Job description

Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, hard-working people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products! The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Join us to help deliver groundbreaking Apple products! In this role, you will be responsible for all aspects of timing including working with the implementation and RTL teams on timing changes, helping with construction/modify timing flows, timing analysis, and timing closure.

Description

As the CPU Design Timing Engineer, you will be responsible for the timing closure of the project.

Responsibilities include but are not limited to:
• Working with the CAD team to develop the timing flow that will be used on the project including scripting to improve analysis flows and engineer efficiency.
• Work extensively with CPU micro-architects and Implementation engineers to drive timing closure for the CPU.

Minimum Qualifications

Minimum BS and 3+ years of relevant experience
Experience with static timing analysis, noise analysis, and fixing noise in designs
Experience with variation modeling
Experience with TCL and either Perl or Python

Preferred Qualifications

Prior experience performing timing analysis in high speed digital designs such as CPUs or other similar designs
Experience in a static timing analysis tool such as PrimeTime®/Tempus®
Knowledge of physical design tools and methodology including logic synthesis, PnR, parasitic extraction, and logic equivalence
Understanding of deep sub-micron technologies and scaling trends
Working knowledge of CPU microarchitecture
Possess data parsing, analysis and representation/plotting skills

About this role

Summary

Manage and analyze timing closure for CPU designs, collaborating with CAD and architecture teams.

Job title

CPU Design Timing Engineer

Experience level

3+ years

Minimum experience

3+ years exp

Industry

technology

Location requirements

Santa Clara, on-site; remote not specified

Salary

Not specified

Management role

No

Skills & keywords

Required skills

static timing analysisnoise analysisnoise fixingvariation modelingTCLPerlPython

Preferred skills

cpu microarchitecturehigh speed digital designPrimeTimeTempusphysical design toolsdeep sub-micron technologydata analysis

Specializations

timing analysisdigital designcpustatic timing analysisphysical design
Locations

Structured locations inferred from the posting.

Santa Clara, CA, USA

On-site City