CPU Design Timing Engineer

Imagine what you could do here! At Apple, new ideas have a way of becoming extraordinary products, services and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, hardworking people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Join us to help deliver the next groundbreaking Apple product! In this role, you will be responsible for all aspects of timing including working with the implementation and RTL teams on timing changes, helping with constructing and modify timing flows, timing analysis, and timing closure.

Description

As a CPU Design Timing Engineer, you will be responsible for the timing closure of the project. Responsibilities include but are not limited to:

• Working with the CAD team to develop the timing flow that will be used on the project including scripting to improve analysis flows and engineer efficiency
• Working extensively with CPU micro-architects and implementation engineers to drive timing closure for the CPU

Minimum Qualifications

Minimum BS and 3+ years of relevant industry experience
Experience with script writing and debugging in one or more of the following languages: TCL, Perl, Python

Preferred Qualifications

Implementation experience on high performance CPU designs
Working knowledge of CPU microarchitecture including common critical loops for timing and understanding of low power microarchitecture and implementation techniques for CPUs
Good understanding of physical design tools and methodology including but not limited to physically aware synthesis and place & route tools and flows, extraction, and other analysis flows, and physical design verification (LEC, DVS, etc.)
Experience working on timing for 1 ghz+ designs, including how to handle multiple clock and power domains
Experience with one of the following static timing tools: Primetime or Tempus
Experience with cross talk, noise, OCV, uncertainty, and derate methodology