CAD Engineer - PDV

Austin Beaverton Until 9/22/2026 10+ years exp First posted July 24, 2026 Last posted July 24, 2026
Job description

Do you love building elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you’ll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You’ll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions! Joining this group means you’ll be responsible for crafting and building the technology that fuels Apple’s devices. Together, you and your team will enable our customers to do all the things they love with their devices. As a member of our CAD team, you will architect, develop, maintain and improve physical design verification (PDV) flows. The role requires you to work on flow and runset development for various technology nodes and tool sets. Working alongside the CAD team, you will be collaborating with the custom digital/analog/mixed-signal design, physical design (PD) and chip integration teams. With good understanding of design rule checks (DRC) and layout versus schematic (LVS) runsets, you will develop rule decks from scratch and/or modify existing ones. You will also have opportunities to develop ML/LLM based automations and solutions.

Description

-Develop, improve and maintain various aspects of physical verification flow and methodology
-Coordinate the effort of validating flows, improving for custom checks and data generation
-Work with the design and PD teams to facilitate the chip design process
-Code custom PDV rule decks such as Electrical rule checks (ERC) and Programmable ERCs
-Collaborate with tool vendors and foundries for PDK performance enhancements

Minimum Qualifications

Minimum requirement of BS +10 years of relevant industry experience.

Preferred Qualifications

Previous industry experience in Silicon chip design flows
Tapeout support and IP/SOC level PDV debug experience in various technology nodes
Expert in Calibre/ICV runset coding for DRC/LVS/ERC/MFILL
Scripting skills in programming languages such as Python, Perl, Tcl, Shell, Makefile or C
Experience with flow automation and development in advanced nodes.
Rule coding in PERC is a plus.
Knowledge of ML/LLM is a plus.
Knowledge of parasitic extraction, SKILL coding, and PnR tools is a plus.

About this role

Summary

Design and improve physical verification flows, code rule decks, collaborate with teams, and develop automations.

Job title

CAD Engineer - PDV

Experience level

10+ years

Minimum experience

10+ years exp

Industry

software

Location requirements

Candidates must be in Austin, Beaverton, San Diego, or Sunnyvale; remote not specified.

Salary

Not specified

Management role

No

Skills & keywords

Required skills

Calibre/ICVPythonPerlTclShell

Preferred skills

ML/LLMparasitic extractionPnR toolsRule coding in PERC

Specializations

physical verificationICVDRCLVSrule decks
Locations

Structured locations inferred from the posting.

Austin, TX, USA

On-site City

Beaverton, OR, USA

On-site City

San Diego, CA, USA

On-site City

Sunnyvale, CA, USA

On-site City