ASIC Engineering Technical Leader

Cisco Systems, Inc.

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Thalwil, Switzerland Until 9/14/2026 12+ years exp First posted July 16, 2026 Last posted July 16, 2026
Job description

Meet the Team

At Cisco, our Silicon and Optics teams are redefining the economics and architecture of the internet. The IP&COT team in Thalwil, Switzerland, is at the forefront of this innovation, developing cutting-edge ASIC technologies that power Cisco's next-generation platforms. We are a dynamic, multi-disciplined engineering group dedicated to pushing the boundaries of power, performance, and area (PPA) optimization. By joining us, you will collaborate with industry-leading experts to design and deliver high-volume, premium-quality ASIC subsystems. Here, your work will directly influence the future of networking silicon, driving solutions that connect and empower the world.

Your Impact

As an ASIC Engineering Technical Leader, you will define, design, and verify high-performance ASIC subsystems deployed across a range of Cisco platforms. You will oversee the architecture and design of complex analog and mixed-signal circuits, driving innovative solutions and establishing robust verification strategies. By collaborating with cross-functional teams, you will influence packaging and hardware requirements to ensure all power, performance, and area goals are met. Your technical expertise will guide the development of reusable code methodologies, physical design functions, and advanced digital design flows, ultimately shaping the future of our high-volume ASIC releases.

Minimum Qualifications

  • Bachelors + 12 years of related experience, or Masters + 8 years of related experience, or PhD + 5 years of related experience, or equivalent related work experience

  • Extensive experience in high-frequency CMOS circuit design and custom analog and mixed-signal circuit design.

  • Proficiency with the Cadence Virtuoso CAD design environment, including custom layout, DRC, LVS, and parasitic extraction.

  • Strong programming skills utilizing languages such as Skill, VerilogA, Tcl, Perl, Python, Matlab, or C.

Preferred Qualifications

  • Experience in high-speed wireline SerDes design, signal processing, and communication systems.

  • Familiarity with digital design flow (synthesis and P&R) and additional CAD tools (Siemens/Mentor, Synopsys).

  • Experience with coil design using EM field simulators (EMX, Momentum, HFSS) and knowledge of packaging technology.

  • Hands-on experience with measurement equipment and in-depth knowledge of version and project management tools (e.g., SOS, Jira).

  • A strong portfolio of publications and patents, with a proven ability to collaborate effectively within a multi-disciplined engineering team.

Why Cisco? 

At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.

Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. 

We are Cisco, and our power starts with you. 

About this role

Summary

Lead ASIC design, verification, and architecture for high-performance silicon.

Job title

ASIC Engineering Technical Leader

Experience level

12+ years

Minimum experience

12+ years exp

Industry

technology

Location requirements

Thalwil, Switzerland; remote work not specified

Salary

Not specified

Management role

No

Skills & keywords

Required skills

CMOS circuit designCadence VirtuosoVerilogATclPython

Preferred skills

high-speed SerDesdigital design flowEM field simulatorsmeasurement equipmentproject management

Specializations

ASICanalogmixed-signalCMOShigh-speed SerDes
Locations

Structured locations inferred from the posting.

Thalwil, Switzerland

Work arrangement unknown City