ASIC Design Verification Engineer

Broadcom Corporation

US-CA Irvine Alton Parkway Bldg 2 US-MA-Andover-Brickstone Square-Suite 101 Until 8/22/2026 12+ years exp H-1B sponsor history First posted June 19, 2026 Last posted June 19, 2026

Job description

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Job Description:

Would you like to become part of a stable team developing silicon products for Ethernet systems in the Cloud? Come join this team creating devices that accelerate AI/ML workflows! This team develops high throughput Ethernet solutions that deliver unprecedented performance at critically important power efficiency.

We are looking for highly skilled and efficient Constrained Random Design Verification engineers that want to verify new designs that can evolve rapidly at every generation in a very dynamic market using industry proven methodologies using System Verilog and UVM. You can become a member of an extremely skilled and efficient group of engineers.

This is a rare opportunity to be part of a team that leads products for a new line of devices. The candidate will work with our worldwide design and architecture teams to develop leading edge products. All aspects of Design Verification will be involved, along with opportunities for technical leadership.

Skills: Self motivated personality with a strong presence to do things right. Need to have a strong sense of teamwork and ability to work well with other. Constrained random verification methodologies with experience driving completion via coverage closure.

Preferable to have skills with SV and UVM, well versed in OOP

Tools/Languages: System Verilog (TB structures - Class, SVA, etc.), UVM, VCS, Incisive, Scripting skills a + (Python, Perl, ...)
Experience: Bachelors and 12+ years of related experience or Masters degree and 10+ years of related experience or PhD and 3+ years of related experience

Additional Job Description:

Compensation and Benefits

The annual base salary range for this position is $129,400.00 - $207,000.00.
 

This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.

Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.

Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.

If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

About this role

Summary

Verify ASIC designs for Ethernet systems using System Verilog and UVM methodologies.

Job title

ASIC Design Verification Engineer

Experience level

12+ years

Minimum experience

12+ years exp

Industry

semiconductors

Location requirements

Multiple US locations, remote work not specified

Salary

$129k–$207k

Visa sponsorship

H-1B sponsor history

Management role

Skills & keywords

Required skills

System VerilogUVMcoverage closureSVAVCSIncisivePythonPerl

Preferred skills

SVOOP

Specializations

verificationsystem verilogUVMcoverage closure

Locations

Structured locations inferred from the posting.

Unknown location

On-site

Andover, MA, USA

On-site City

Broomfield, CO, USA

On-site City