ASIC design and verification enginner

Capitolinternationalservicesltd

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Belgium, be on site Until 8/21/2026 First posted March 18, 2026 Last posted March 18, 2026
Job description

For one of our clients in Belgium, we are looking for a hardware engineer with extensive experience in ASIC design and verification. It is for an initial 6 month contract + extensions, and fully on-site at the client's premises. 

- At least 5 years experience of ASIC design & verification 

- Block level design and specification writing

- Debugging RTL at the block level 

- SystemVerilog and UVM - Fluent English

About this role

Summary

hardware engineer with ASIC design and verification expertise, block level debugging, SystemVerilog, UVM

Job title

ASIC design and verification enginner

Experience level

5+ years

Industry

technology

Location requirements

on-site in belgium, remote not allowed

Salary

Not specified

Management role

No

Skills & keywords

Required skills

ASIC designverificationSystemVerilogUVM

Preferred skills

None specified

Specializations

ASIC designverificationRTLSystemVerilogUVM
Locations

Structured locations inferred from the posting.

Belgium, WI 53004, USA

On-site City