Analog layout engineers

This role is for one of the Weekday's clients

Salary range: Rs 1200000 - Rs 2500000 (ie INR 12- 25 LPA)

Min Experience: 3+ years

Location: Bengaluru
JobType: full-time

We are looking for a skilled and detail-oriented Analog Layout Engineer with 3–5 years of experience in custom IC layout design and physical implementation. The ideal candidate will have strong hands-on experience in analog and mixed-signal layout, with exposure to advanced semiconductor process nodes. Experience in 16FF custom layout will be highly valued.

The role involves working closely with circuit designers and physical design teams to translate schematic designs into high-quality, manufacturable layouts while ensuring performance, reliability, and adherence to foundry design rules.

Requirements

Key Responsibilities

• Develop high-quality custom analog and mixed-signal layouts based on schematics, design specifications, and layout guidelines.
• Perform block-level and top-level layout implementation for analog circuits such as amplifiers, current mirrors, bandgaps, references, ADC/DAC blocks, PLL components, and other mixed-signal circuits.
• Create and optimize layouts using industry-standard custom IC layout tools.
• Apply advanced layout techniques including common-centroid, interdigitation, symmetry, matching, shielding, guard rings, dummy devices, and sensitive-node isolation.
• Work extensively on 16FF custom layout and support physical implementation in advanced process technologies.
• Perform Design Rule Check (DRC), Layout Versus Schematic (LVS), and other physical verification activities.
• Identify and resolve layout-related issues, including DRC/LVS violations, parasitic concerns, connectivity errors, and density-related issues.
• Collaborate with circuit designers to understand performance requirements and implement layout solutions that minimize parasitic effects and improve circuit matching.
• Support parasitic extraction (PEX) and analyze extracted results to identify layout-induced performance degradation.
• Optimize layouts for area, power, signal integrity, matching, and overall circuit performance.
• Follow foundry-specific design rules, technology requirements, and internal layout methodologies.
• Participate in design reviews, layout reviews, and cross-functional discussions with design, verification, and physical design teams.
• Maintain accurate documentation of layout decisions, verification results, and design changes.

Required Skills

• 3–5 years of professional experience in Analog Layout Engineering.
• Strong hands-on experience in custom analog and mixed-signal IC layout.
• Good understanding of semiconductor fabrication processes and CMOS device structures.
• Experience with Cadence Virtuoso or equivalent custom layout design environments.
• Strong knowledge of DRC, LVS, ERC, PEX, and physical verification methodologies.
• Understanding of layout-dependent effects, parasitics, device matching, and analog layout best practices.
• Ability to interpret schematics and understand transistor-level circuit connectivity.
• Good understanding of advanced-node layout challenges and design constraints.
• Strong analytical and debugging skills.

Good-to-Have Skills

• Hands-on experience with 16FF custom layout.
• Experience working on advanced technology nodes such as 7nm, 10nm, 12nm, or 16nm.
• Exposure to FinFET-based layout methodologies.
• Experience with high-performance analog, mixed-signal, or RF circuits.
• Knowledge of advanced matching, shielding, noise-isolation, and electromigration techniques.
• Experience with automation or scripting for layout-related tasks.
• Familiarity with foundry PDKs and advanced physical verification flows.
• Experience collaborating with global semiconductor design teams.

Education

Bachelor’s or Master’s degree in Electronics Engineering, Electrical Engineering, Microelectronics, VLSI, or a related field.

Ideal Candidate

The ideal candidate is a technically strong Analog Layout Engineer who combines excellent attention to detail with a solid understanding of transistor-level design and physical implementation. Candidates with direct 16FF custom layout experience and the ability to independently execute complex analog layout blocks will be preferred.