DV - Staff (+) Verification Engineer - AMS modeling
Eliyan
Apply to this job Bay Area, Vancouver or Toronto on site Until 8/23/2026 5+ years exp H-1B sponsor history First posted May 21, 2026 Last posted May 21, 2026
Job description
Join the leading chiplet startup! As an Eliyan Verification Engineer, you will be working at a fast-paced early-stage startup creating technologies that fuel tomorrow's chiplet-based systems with best-in-class power, area, manufacturability, and design flexibility. In this role you will lead the verification of Serdes. You will be developing state-of-the-art AMS systemVerilog models (RNM) for best-in-class PHYs. You will own verification of AMS SystemVerilog models. This is a hands-on technical role. You'll work with analog team, look at schematics and write the RNM models. We offer a fun work environment with excellent benefits. We offer a fun work environment with excellent benefits. ONSITE M-F.
Key Responsibilities:
- Develop and execute RNM AMS model for best in class PHYs.
- Make sure the quality of models reflects schemetics.
- Write and debug SystemVerilog/UVM compliant test cases
- Collaborate with design team to ensure design quality
- Expertise to understand analog blocks.
Required Qualifications:
- 5+yrs relevant experience
- BS in EE or related field.
- Deep analog design expertise
- Knowledge of SystemVerilog, test environment and assertion coding
- Experience in verifying mixed signal IPs
Preferred Qualifications:
- Experience with Formal verification with Jasper Gold or vc-formal
- Python/Perl/Tcl scripting for design verification
About this role
Summary
Verify mixed signal IPs, develop AMS models, and collaborate with design teams in a fast-paced startup environment.
Job title
verification engineer
Experience level
5+ years
Minimum experience
5+ years exp
Industry
semiconductors
Location requirements
onsite in bay area, vancouver, or toronto, no remote
Salary
Not specified
Visa sponsorship
H-1B sponsor history
Management role
No
Skills & keywords
Required skills
SystemVerilogtest environmentassertion codinganalog design
Preferred skills
formal verificationjasper goldvc-formalpythonperltcl
Specializations
AMSSystemVerilogSerdesanalogmixed signal
Locations
Structured locations inferred from the posting.
Bay Area, Corpus Christi, TX, USA
On-site City
Vancouver, BC, Canada
On-site City
Toronto, ON, Canada
On-site City